The present invention relates to liquid crystal display devices for use in, for example, monitors for personal computers and OA (office automation) and FA (factory automation) equipment, and display panels for portable information terminals.
Conventionally, liquid crystal display devices using nematic liquid crystals have been widely used as segment type liquid crystal display devices for use in watches and electronic calculators. In recent years, such a liquid crystal display device has expanded its market and been used as various types of displays for word processors, personal computers, navigation systems, etc., because of its thin, light weight, low power consuming characteristics. In particular, an active matrix liquid crystal display device in which active elements such as TFTs (thin film transistors) are used as switching elements and pixels are arranged in a matrix, has been noted.
Compared to, for example, a CRT (cathode ray tube), the above-mentioned liquid crystal display devices have advantages that they can be made much thinner (in depth), achieve a full color display easily, and consume less power. Therefore, such liquid crystal display devices are suitably used as displays of notebook type personal computers, portable television sets, digital cameras, digital video cameras, and so on.
A conventional transmissive type active matrix liquid crystal display device includes a light transmitting active matrix substrate, a counter substrate having a common electrode formed thereon, and a liquid crystal. An active matrix circuit constituted by a TFT is formed on the active matrix substrate. The counter substrate is disposed to face the active matrix substrate, and a liquid crystal is sandwiched between the active matrix substrate and the counter substrate.
FIG. 11 is a circuit diagram showing schematically an example of the active matrix circuit on the active matrix substrate. A plurality of pixel electrodes 31 are arranged in a matrix on the active matrix substrate. Usually, several hundred pixel electrodes 31 are arranged respectively in rows and columns.
Besides, a common electrode 32 is formed on the counter substrate so that the common electrode 32 faces the pixel electrodes 31 with a liquid crystal layer therebetween. A voltage is applied to the liquid crystal layer by the pixel electrodes 31 and common electrode 32. In general, the common electrode 32 is formed on the substantially entire surface of the counter substrate.
Moreover, TFTs 33 as active elements functioning as switching means for selectively driving the pixel electrodes 31 are formed on the active matrix substrate and connected to the pixel electrodes 31. Furthermore, in order to provide a color display, a color filter layer (not shown) including, for example, red, green and blue filters is placed on the counter substrate or the active matrix substrate.
Scanning lines 34 are connected to the gate electrodes of the TFTs 33, while signal lines 35 are connected to the source electrodes thereof. The scanning lines 34 and signal lines 35 are arranged such that they run around the pixel electrodes 31 arranged in a matrix and cross each other at right angles. By inputting gate signals through the scanning lines 34, the TFTs 33 are driven under control. Further, when the TFTs 33 are driven, data signals are input to the pixel electrodes 31 through the signal lines 35. Incidentally, scanning signal input terminals 34a are connected to the end sections of the scanning lines 34, and data signal input terminals 35a are connected to the end sections of the signal lines 35.
Besides, the drain electrodes of the TFTs 33 are connected to the pixel electrodes 31 and the accumulation capacitors 36. The accumulation capacitors 36 are connected to reference signal lines 37, respectively. The accumulation capacitors 36 perform the function of maintaining a voltage applied to the liquid crystal layer.
In the active matrix liquid crystal display device as described above, the liquid crystal layer sandwiched between the active matrix substrate and counter substrate has a thickness of usually between 4.3 and 4.5 xcexcm on average, and a liquid crystal capacitor is formed by the pixel electrodes 31, common electrodes 32 and liquid crystal layer. Additionally, the accumulation capacitors 36 are connected to the liquid crystal capacitor in parallel.
In the above-mentioned structure, as illustrated in FIG. 7, the liquid crystal capacitor and the accumulation capacitor 36 are connected to the reference signal line 37 in series. Here, the capacitance of the liquid crystal capacitor is represented by Clc, and the capacitance of the accumulation capacitor 36 is represented by Cs. Then, the series capacitance of the liquid crystal capacitor and the accumulation capacitor 36 per pixel is given by (Clcxc3x97Cs)/(Clc+Cs).
For instance, in the case of a liquid crystal display device with a 13.3-inch display and XGA (extended graphics array) of (1024xc3x97768), the series capacitance per pixel is around 0.33xc3x97Clc. When N pieces of such a series capacitance are provided for each reference signal line 37, the total load capacitance per reference signal line 37 is around 0.33xc3x97Nxc3x97Clc.
Such a load capacitance would cause a signal delay. In order to reduce the signal delay, a connecting line 38 for connecting the reference signal lines 37 to each other may be provided as shown in FIG. 11.
Here, the structure of the TFT 33 will be explained in great detail. FIG. 10 is a cross sectional view showing a schematic structure in the vicinity of the TFT 33. A gate electrode 40 is formed on a transparent insulating substrate 39, and a gate insulating film 41 is formed to cover the gate electrode 40. A semiconducting film 42 is formed on the gate electrode 40 with the gate insulating film 41 therebetween. A channel protecting film 43 is formed at the top center of the semiconducting film 42. A source electrode 44s made of a microcrystal n+ silicone layer is provided on the source side of the channel protecting film 43 and semiconducting film 42. Similarly, a drain electrode 44d made of a microcrystal n+ silicone layer is provided on the drain side thereof.
A metallic layer 45s serving as a source line is connected to the source electrode 44s, while a metallic layer 45d for forming a drain line is connected to the drain electrode 44d. 
The surface of the TFT 33 having the abovementioned structure is covered with an inter-layer insulating film 46. Further, a transparent conductive film for forming a pixel electrode 31 is placed on the inter-layer insulating film 46. The pixel electrode 31 is connected to the metallic layer 45d as the drain line of the TFT 33 through a contact hole 47. Moreover, on the pixel electrodes 31, although it is not shown in the drawings, an alignment film for aligning the liquid crystal is formed substantially uniformly over the entire display area.
As the inter-layer insulating film 46, an inorganic thin film such as SiN has been conventionally used. The SiN film is deposited with a film thickness of more than around 300 nm by, for example, a CVD (chemical vapor deposition) method.
Moreover, as an example of a liquid crystal display device having a structure different from the above-mentioned structure of the liquid crystal display device, Japanese laid-open patent publication No. (Tokukaihei) 7-128687 (published on May 19, 1995) discloses a liquid crystal display device in which the signal lines are formed on the counter substrate. In this liquid crystal display device, since the scanning lines and the signal lines are formed on different substrates, they do not intersect each other on a single substrate. As a result, the rate of occurrence of defects due to a short circuit between the scanning line and the signal line is reduced, thereby achieving an improved yield.
FIG. 12 is a circuit diagram showing schematically an example of a circuit formed on the pixel substrate of the liquid crystal display device including the signal lines formed on the counter substrate. A plurality of three-terminal switching elements 48 made from amorphous silicone semiconductors are arranged in a matrix on the pixel substrate. One terminal of each switching element 48 is connected to a scanning line 49, one of the other terminals is connected to a reference signal line 50, and the remaining terminal is connected to a pixel electrode 51.
Incidentally, counter electrodes 52 and signal lines 53 are formed on the counter substrate.
Each scanning line 49 has a scanning signal input terminal 49a at one of the end sections thereof. Moreover, the reference signal lines 50 are connected to each other with a connecting line 54. Furthermore, a reference signal input terminal 50a is connected through a leading line 55 connected to the connecting line 54.
In order to prevent the connecting line 54 from crossing the scanning lines 49 and reference signal lines 50, the connecting line 54 is arranged on a side opposite to the side whereon the scanning signal input terminals 49a are positioned. Besides, for the purposes of simplifying the packaging, the reference signal input terminal 50a is provided at an end of a line into which the scanning signal input terminals 49a are arranged.
In the above-mentioned structure, when the switching element 48 is in an ON state, a liquid crystal capacitor is connected to the reference signal line 50 as shown in FIG. 8. Note that, similarly to the above, the capacitance of the liquid crystal capacitor is denoted as Clc. When N pieces of liquid crystal capacitors are connected to a single reference signal line 50, the load capacitance per reference signal line 50 is around Nxc3x97Clc. Thus, the load capacitance is larger than that of the above-mentioned liquid crystal display device having the structure shown in FIG. 7.
On the other hand, when the switching element 48 is in an OFF state, the liquid crystal capacitor and a capacitor between adjacent pixels are connected in series to the reference signal line 50 as shown in FIG. 9. The capacitor between adjacent pixels means a capacitance between adjacent pixels in the proximity of the reference signal line 50, and the value of the capacitance is denoted as Cbp. In this case, the series capacitance of the liquid crystal capacitance and the capacitance between adjacent pixels per pixel is given by (Clcxc3x97Cbp)/(Clc +Cbp).
For instance, for a liquid crystal display device with a 13.3-inch display and XGA (1024xc3x97768), the series capacitance per pixel is around 0.03xc3x97Clc. Besides, when N pieces of such series capacitors are connected to a single reference signal line 50, the total load capacitance with respect to the single reference signal line would be around 0.03xc3x97Nxc3x97Clc.
In a liquid crystal display device having the structure shown in FIG. 11, when the inter-layer insulating film 46 is formed by depositing a transparent insulating film such as SiNx, SiO2, and TaOx, by the CVD method or sputtering method, the irregularity on the surface of the metallic film as the under layer reflects on the inter-layer insulating film 46 as shown in FIG. 10.
In addition, since the scanning lines 34 and signal lines 35 are arranged to intersect each other on the insulating substrate 39, an extremely large number of intersections of the scanning lines 34 and signal lines 35 are present on the insulating substrate 39.
Therefore, at the large number of intersections of the scanning lines 34 and signal lines 35, the signal lines 35 are placed on the scanning lines 34, so that a difference in level is produced. Thus, in such an intersection, the inter-layer insulating film 46 tends to be cracked, and the signal line 35 above the interlayer insulating film 46 tends to be cut during the production. Alternatively, in the event where a pinhole-like defect is present in the inter-layer insulating film 46, a short-circuit occurs between the signal line 35 as the upper layer and the scanning line 34 as the lower layer, resulting in a lowered yield.
Moreover, there are possibilities that a new crack is produced at such an intersection with the passage of time and the crack produced during the production becomes larger, due to the influence of a film deposition residual force and so on. Thus, there is a possibility that defects occur in the products after putting the products on the market, resulting in a lowering of the reliability.
Furthermore, in order to decrease the signal delay, for example, it is preferred to arrange the line width of the reference signal line 37 to be wider than the line width of the scanning line 34. However, if the line width of the reference signal line 37 is increased too much, the aperture ratio of the liquid crystal display device is lowered and the brightness is lowered. The reason for such a lowering is that the reference signal line 37 is formed by a light blocking metallic material with low resistivity as so to achieve a low resistance.
Alternatively, the signal delay cay be decreased by providing the connecting line 38 as described above. However, since the load capacitance with respect to the reference signal line 37 is substantially uniform at a relatively high value irrespective of whether the TFT 33 is in an ON state or an OFF state. Thus, the provision of the connecting line 38 is insufficient to produce the effect of decreasing the signal delay.
In contrast, in a liquid crystal display device having the structure shown in FIG. 12, since the signal lines 53 are formed on the counter substrate, defects such as a short-circuit between the signal lines 53 and the scanning lines 49 do not occur. However, none of Japanese laid-open patent publication No. (Tokukaihei) 7-128687 (published on May 19, 1995) and other prior art documents disclose anything about the change in the load capacitance of the reference signal line 50 according to the ON or OFF state of the switching element 48 and the structure of arranging the connecting line 54 in light of the change in the load capacitance.
Objects of the present invention are to provide a liquid crystal display device capable of reducing the occurrence of a short circuit between lines on a substrate and decreasing the signal delay due to a load capacitance, and a method for producing a liquid crystal display device at an excellent yield.
In order to achieve the above object, a liquid crystal display device of the present invention includes:
a pixel substrate having a plurality of pixel electrodes arranged in a matrix, a plurality of reference signal lines connected to the pixel electrodes through switching elements, and a plurality of scanning lines, each of the scanning lines having a scanning signal input terminal at one of ends thereof, each of the switching elements being switched according to a scanning signal input through the scanning signal input terminal;
a counter substrate disposed to face the pixel substrate, the counter substrate being provided with a plurality of counter electrodes arranged to face the pixel electrodes and a plurality of data signal lines that intersect the scanning lines with a liquid crystal layer therebetween;
a first connecting line for connecting the reference signal lines to each other, the first connecting line being located outside of a region where the pixel electrodes are arranged and in proximity of the other end of each of the scanning lines; and
at least one second connecting line for connecting the reference signal lines to each other, the second connecting line being located outside of the region where the pixel electrodes are arranged and in proximity of the scanning signal input terminals.
According to this structure, the pixel substrate faces the counter substrate with the liquid crystal layer therebetween, the pixel electrodes, scanning lines and switching elements are formed on a substrate different from a substrate having the data signal lines formed thereon, and the scanning lines and data signal lines cross each other with the liquid crystal layer therebetween.
The switching element is switched according to a scanning signal applied to the scanning line through the scanning signal input terminal. As a result, a reference signal is supplied to the pixel electrode, while a data signal is supplied to the counter electrode through the data signal line. Thus, by supplying the reference signals and data signals to the pixel electrodes and the counter electrodes, respectively, a liquid crystal display according to the data signals is provided.
By the way, in the case where only a single connecting line for connecting the reference signal lines to each other is provided (where the reference signals are supplied through only a single line), the load capacitance of the reference signal line varies according to a switching state (ON or OFF) of the switching element, and therefore the reference signal is delayed due to the charging of the load capacitance.
Hence, in the above-mentioned structure, the first connecting line arranged in the proximity of the other end of each scanning line and the second connecting line arranged in the proximity of each scanning signal input terminal are positioned outside of the region where the pixel electrodes are formed. The first and second connecting lines are positioned on the opposite sides with respect to the region where the pixel electrodes are formed. Therefore, the reference signal is supplied to each reference signal line through both connecting lines (first and second connecting lines).
In this case, the signal delay becomes maximum in the vicinity of the center of each reference signal line. In the case where only a single reference signal line is provided, the signal delay becomes maximum at an end of each reference signal line located on the opposite side to the reference signal input side. Thus, when the reference signal is supplied through the first and second connecting lines, the resistance and electrostatic capacitance from the input terminals (first and second connecting lines) of the reference signal are reduced to about xc2xd of those when the reference signal is supplied through only a single connecting line. Consequently, the signal delay due to the charging of the load capacitance of the reference signal line is decreased to about xc2xc.
The load capacitance of the reference signal line is much larger when the corresponding switching element is switched ON than when the switching element is switched OFF. However, according to the abovementioned structure, switching elements in the OFF state are connected to reference signal lines located on each side of a reference signal line connected to a switching element in the ON state, and these three reference signal lines are connected to each other with the first and second connecting lines. Hence, the load capacitance of the reference signal line connected to the switching element in the ON state is decreased on the whole, and the signal delay due to the load capacitance can be certainly reduced by an amount corresponding to the decrease in the load capacitance.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.